Pixel array substrate

ABSTRACT

A pixel array substrate including a substrate, a first signal line, a second signal line, a third signal line, a first active element and a conductive pattern is provided. The first signal line and the second signal line are disposed on the substrate and intersect with each other. The third signal line is disposed on the substrate and overlapped with the second signal line. The extending direction of the third signal line is parallel to the extending direction of the second signal line. The first active element is electrically connected to the first signal line. The first active element includes a semiconductor pattern, a first gate and a second gate. The semiconductor pattern is located between the first gate and the second gate. The first gate is overlapped with the second gate and connected to the third signal line. The second gate is connected to the first gate via the conductive pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefits of U.S. provisionalapplication Ser. No. 62/717,260, filed on Aug. 10, 2018, and Taiwanapplication serial no. 108111006, filed on Mar. 28, 2019. The entiretyof each of the above-mentioned patent applications is herebyincorporated by reference herein and made a part of this specification.

BACKGROUND Technical Field

The present invention relates to a pixel array substrate, and moreparticularly to a low-power consuming pixel array substrate.

Description of Related Art

With the popularity of the display panels, the display panels can befound on home TVs, e-sports screens, large outdoor billboards, publicmessage screens in stores, and even portable or wearable electronicdevices. In recent years, in addition to the pursuit of functionalityand appearance, energy-saving devices have gradually become one of thekey projects in product development. For example, a notebook computerthat is dedicated to e-sports needs to be equipped with a high framerate display panel. However, the power consumption of such high framerate display panel is higher than that of a general display panel, suchthat the endurance of the notebook computer with the high frame ratedisplay panel is reduced when it is powered by a battery.

In order to solve the above problem, the idea of the display screen tobe locally updated has arisen, that is, the display panel can update thescreen at different frequencies for the static image zone and thedynamic image zone of the display screen. For example, the pixel locatedin the static image zone can be driven by the update frequency of 1 Hz,and the pixel located in the dynamic image zone can be driven by theupdate frequency of 60 Hz, which can effectively reduce the powerconsumption of the display panel, thereby improving the endurance of themobile device. However, this technology needs to be configured with anadditional multiplex circuit on the display panel, which may decreasethe aperture ratio of the pixel or reduce the layout space of the pixelcircuit.

SUMMARY

The invention provides an energy-saving pixel array substrate, which hasa good design margin of a driving circuit.

The pixel array substrate of the present invention includes a substrate,a first signal line, a second signal line, a third signal line, a firstactive element, and a conductive pattern. The first signal line and thesecond signal line are disposed on the substrate and intersect eachother. The third signal line is disposed on the substrate. The extendingdirection of the third signal line is parallel to the extendingdirection of the second signal line. The third signal line is overlappedwith the second signal line. The first active element is electricallyconnected to the first signal line. The first active element includes asemiconductor pattern, a first gate, and a second gate. Thesemiconductor pattern is located between the first gate and the secondgate. The first gate is overlapped with the second gate and is connectedto the third signal line. The second gate is connected to the first gatethrough the conductive pattern.

Based on the above, in the pixel array substrate of one embodiment ofthe present invention, the pixel structures connected to the same firstsignal line can be respectively driven at different update frequenciesthrough the settings of the third signal line, the first gate and thesecond gate, which helps to reduce the power consumption of the pixelarray substrate. Further, by overlapping the third signal line with thesecond signal line, the aperture ratio of the pixel structure and thelayout space of the driving circuit can be increased. Moreover, in thefirst active element, the semiconductor pattern is interposed betweenthe first gate and the second gate, thereby effectively improving theoperating electrical properties of the active element.

In order to make the aforementioned features and advantages of thedisclosure more comprehensible, embodiments accompanied with drawingsare described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a pixel array substrate according to anembodiment of the present invention;

FIG. 2 and FIG. 3 are schematic cross-sectional views of two differentpositions on the pixel array substrate of FIG. 1.

FIG. 4 is a top view of a pixel array substrate according to anotherembodiment of the present invention;

FIG. 5 is a top view of a pixel array substrate according to stillanother embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

The term “about,” “approximately,” “essentially” or “substantially” asused herein is inclusive of the stated value and means within anacceptable range of deviation for the particular value as determined bythose of ordinary skill in the art, considering the measurement inquestion and the error associated with measurement of the particularquantity (i.e., the limitations of the measurement system). For example,“about” may mean within one or more standard deviations, or within, forexample, ±30%, ±20%, ±15%, ±10%, ±5% of the stated value. Moreover, arelatively acceptable range of deviation or standard deviation may bechosen for the term “about,” “approximately,” “essentially” or“substantially” as used herein based on measuring properties, cuttingproperties or other properties, instead of applying one standarddeviation across all the properties.

In the accompanying drawings, thicknesses of layers, films, panels,regions and so on are exaggerated for clarity. It should be understoodthat when an element such as a layer, film, region or substrate isreferred to as being “on” or “connected to” another element, it can bedirectly on or connected to the other element, or intervening elementsmay also be present. In contrast, when an element is referred to asbeing “directly on” or “directly connected to” another element, thereare no intervening elements present. As used herein, the term“connected” may refer to physically connected and/or electricallyconnected. Therefore, the electrical connection may be refer anintervening elements exist between two elements.

In the disclosure, to facilitate understanding, positions of a sourceand a drain in a transistor in the drawings are exemplary and notintended to be limiting. The reason is that the source and the drain inthe transistor may change with current direction, or may differdepending on whether the transistor is an N-type transistor or a P-typetransistor.

Reference will now be made in detail to the present preferredembodiments of the disclosure, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numeralsare used in the drawings and the description to refer to the same orlike parts.

FIG. 1 is a top view of a pixel array substrate 10 according to anembodiment of the present invention. FIG. 2 and FIG. 3 are schematiccross-sectional views of two different positions on the pixel arraysubstrate 10 of FIG. 1. FIG. 2 and FIG. 3 correspond to the sectionalline A-A′ and the sectional line B-B′ of FIG. 1, respectively. It shouldbe noted that the first insulating layer 210, the second insulatinglayer 220, the third insulating layer 230 and the fourth insulatinglayer 240 of FIG. 2 are omitted in FIG. 1 for clarity purposes.

In particular, the pixel array substrate of the present invention isapplicable to a display panel, wherein the display panel furtherincludes a display medium (e.g., a liquid crystal material layer, aluminescent material layer) disposed on the pixel array substrate, anddriving electrode covering the display medium. For example, the pixelarray substrates 10 and 20 of FIGS. 1 and 4 may be applied to anon-self-luminescent display panel, such as a liquid crystal displaypanel (LCD panel), and the pixel array substrate 30 of FIG. 5 may beapplied to a self-luminescent display panel, such as an organic lightemitting diode (OLED) panel, a micro-light emitting diode (Micro-LED)panel, and a mini-light emitting diode (Mini-LED) panel, but theinvention is not limited thereto.

Referring to FIG. 1, the pixel array substrate 10 includes a substrate100, a plurality of first signal lines SL1, and a plurality of secondsignal lines SL2. The first signal lines SL1 and the second signal linesSL2 are disposed on the substrate 100 and each first signal line SL1 andeach second signal line SL2 intersect with each other. For example, inthe present embodiment, the first signal line SL1 is, for example, ascan line, and the second signal line SL2 is, for example, a data line,and the extending direction of the first signal line SL1 (i.e., thedirection x) may be substantially perpendicular to the extendingdirection of the second signal line SL2 (i.e., the direction y), but theinvention is not limited thereto.

In the present embodiment, in consideration of conductivity, the firstsignal line SL1 and the second signal line SL2 are generally made of ametal material. However, the present invention is not limited thereto.According to other embodiments, the first signal line SL1 and the secondsignal line SL2 may also be made of other conductive materials, such asan alloy, a nitride of a metal material, an oxide of a metal material,an oxynitride of a metal material, other suitable materials, or astacked layer of a metal material and said other conductive materialsdescribed above. It should be noted that the present invention does notlimit the number of the first signal line SL1 and the second signal lineSL2 by the content disclosed in the drawings. In some embodiments, thenumber of the first signal line SL1 and the second signal line SL2 maybe adjusted depending on the actual design requirements.

Further, the adjacent two first signal lines SL1 cross over the adjacenttwo second signal lines SL2 to define one pixel area PA of the pixelarray substrate 10. The pixel array substrate 10 further includes aplurality of pixel structures PX located in a plurality of pixel regionsPA. Further, the pixel structure PX includes a first active element T1and a pixel electrode PE. The first active element T1 is electricallyconnected to the corresponding first signal line SL1, the correspondingsecond signal line SL2 and the corresponding pixel electrode PE. Inparticular, the first active element T1 may serve as a charging (ordischarging) switch of the pixel electrode PE. For example, when thefirst active element T1 is turned on, the charge transmitted on thesecond signal line SL2 can be transmitted to the pixel electrode PE viathe first active element T1 (i.e., the pixel electrode PE is charged);or when the first active element T1 is turned on, the charge of thepixel electrode PE can be transmitted to the second signal line SL2 viathe first active element T1 (i.e., the pixel electrode PE is discharged.

In this embodiment, the pixel electrode PE may be a transmissiveelectrode, and the material of the transmissive electrode may include ametal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO),aluminum tin oxide (ATO), aluminum zinc oxide (AZO), other suitableoxides, or a stacked layer of at least two of the aforesaid materials.However, the present invention is not limited thereto. In otherembodiments, the pixel electrode PE may be a reflective electrode, andthe material of the reflective electrode may include metal, an alloy, anitride of a metal material, an oxide of a metal material, an oxynitrideof a metal material, other suitable materials, or a stacked layer of ametal material and the aforesaid conductive materials.

Referring to FIG. 1 and FIG. 2, the pixel array substrate 10 furtherincludes a plurality of third signal lines SL3 disposed corresponding tothe plurality of pixel structures PX, respectively. The third signallines SL3 are arranged side by side and located on the substrate 100,and the extending direction of each third signal line SL3 may beparallel to the extending direction of each second signal line SL2. Inparticular, each of the third signal lines SL3 overlaps thecorresponding second signal line SL2 in the normal direction zperpendicular to the substrate 100, which helps to reduce the layoutspace of the pixel driving circuit.

In this embodiment, the second signal line SL2 may completely overlapthe corresponding third signal line SL3 in the normal direction zperpendicular to the substrate 100, and the width W1 of the secondsignal line SL2 in the direction x may be smaller than the width W2 ofthe third signal line SL3 in the direction x. That is, the verticalprojection area of the second signal line SL2 on the substrate 100 maybe smaller than the vertical projection area of the third signal lineSL3 on the substrate 100, but the invention is not limited thereto. Insome embodiments, the second signal line SL2 may partially overlap thecorresponding third signal line SL3 in the normal direction zperpendicular to the substrate 100. In some other embodiments, the widthW1 of the second signal line SL2 in the direction x and the width W2 ofthe third signal line SL3 in the direction x may be substantially equal.Moreover, in the present embodiment, in order to increase the subsequentprocess latitude, the material of the third signal line SL3 may includemolybdenum, molybdenum oxide, or other alloy containing molybdenum.

Further, the first active element T1 includes a semiconductor patternSC, a source S, a drain D, a first gate G1, and a second gate G2. Thesource S and the drain D are electrically connected to the second signalline SL2 and the pixel electrode PE, respectively. In this embodiment,the source S may be a part of the second signal line SL2, but theinvention is not limited thereto. In addition, the first gate G1 and thesecond gate G2 are electrically connected to the third signal line SL3.The first gate G1 overlaps the second gate G2 in the normal direction zperpendicular to the substrate 100, and the semiconductor pattern SC islocated between the first gate G1 and the second gate G2. In thisembodiment, the first active element T1 may further include a third gateG3 connected to the first signal line SL1, and the third gate G3 may bedisposed above the semiconductor pattern SC, but the present inventionis not limited thereto. In other embodiments, the third gate G3 may bedisposed under the semiconductor pattern SC.

Since the first active element T1 has the first gate G1 and the secondgate G2 both electrically connected to the third signal line SL3 and thethird gate G3 electrically connected to the first signal line SL1, inthe pixel array substrate 10, the first active element T1 can be turnedon through the first signal line SL1 and the third signal line SL3, soas to charge or discharge the pixel electrode PE. On the other hand, inthe pixel array substrate 10, the first active element T1 can be turnedoff through at least one of the first signal line SL1 and the thirdsignal line SL3, so that the pixel electrode PE stops charging ordischarging.

For example, the pixel structures PX connected to the same first signalline SL1 (e.g., a scan line) include a first pixel structure and asecond pixel structure. During a scan period, when the third gate G3 ofthe first pixel structure and the third gate G3 of the second pixelstructure are applied with a positive bias through the same first signalline SL1, the first gate G1 and the second gate G2 of the first pixelstructure are applied with another positive bias through thecorresponding third signal line SL3, so that the pixel electrode PE ofthe first pixel structure is charged or discharged through thecorresponding second signal line SL2; at the same time, the first gateG1 and the second gate G2 of the second pixel structure are applied witha negative bias through the corresponding third signal line SL3, so thatthe pixel electrode PE of the second pixel structure cannot be chargedor discharged through the corresponding second signal line SL2.

In other words, the pixel structures PX connected to the same firstsignal line SL1 can be respectively charged (or discharged) at differentupdate frequencies through the settings of the first gate G1, the secondgate G2 and the third signal line SL3. For example, a portion of thepixel structures PX can be driven at an update frequency of 60 Hz, whileanother portion of the pixel structures PX can be driven at an updatefrequency of 1 Hz. As a result, the power consumption of the pixel arraysubstrate is able to be reduced. Moreover, the first active element T1includes the first gate G1 and the second gate G2 disposed on the upperand lower sides of the semiconductor pattern SC, so that the leakagecurrent generated when the active element is turned off can beeffectively reduced.

Referring to FIG. 2, in the embodiment, the method for forming the firstactive element T1 may include the steps of sequentially forming thefirst gate G1, the first insulating layer 210, the semiconductor patternSC, the second insulating layer 220, the second gate G2 and the thirdgate G3, the third insulating layer 230, the source S and the drain D onthe substrate 100. The semiconductor pattern SC includes a first channelregion CR1, a second channel region CR2, a source region SR, and a drainregion D formed by performing the ion doping process with the secondgate G2 and the third gate G3 as masks. The second gate G2 and thesecond channel region CR2 are overlapped with each other in the normaldirection z perpendicular to the substrate 100. The third gate G3 andthe first channel region CR1 overlapped with each other in the normaldirection z perpendicular to the substrate 100. The source region SRoverlaps the third signal line SL3 in the normal direction zperpendicular to the substrate 100. The source S is electricallyconnected to the source region SR through a contact window 225 a formedin the second insulating layer 220 and the third insulating layer 230,and the drain D is electrically connected to the drain region DR througha contact window 225 b formed in the second insulating layer 220 and thethird insulating layer 230. However, the invention is not limitedthereto.

In the present embodiment, the semiconductor pattern SC, the firstinsulating layer 210, the second insulating layer 220, the thirdinsulating layer 230, the first gate G1, the second gate G2, the thirdgate G3, the source S and the drain D may each be implemented by anysemiconductor pattern, any insulating layer, any gate, any source andany drain for the pixel array substrate well known to those of ordinaryskill in the art. And, the semiconductor pattern SC, the firstinsulating layer 210, the second insulating layer 220, the thirdinsulating layer 230, the first gate G1, the second gate G2, the thirdgate G3, the source S and the drain D may each be formed by any methodknown to those of ordinary skill in the art. In particular, in thepresent embodiment, the first insulating layer 210, the secondinsulating layer 220, the third insulating layer 230, and the fourthinsulating layer 240 may respectively be a buffer layer, a gateinsulating layers, an interlayer insulating layer and a planarizationlayer, but the invention is not limited thereto.

As seen from FIG. 2 and FIG. 3, in the present embodiment, the materialsof the first gate G1 and the third signal line SL3 may be the same, andthe materials of the source S, the drain D, and the second signal lineSL2 may be the same. That is, the first gate G1 and the third signalline SL3 may be formed in the same layer, and the source S, the drain Dand the second signal line SL2 may be formed in the same layer, but theinvention is not limited thereto. In some embodiments, the third signalline SL3, the second gate G2 and the third gate G3 may belong to thesame layer.

As seen from FIG. 1 and FIG. 2, the materials of the second gate G2, thethird gate G3 and the first signal line SL1 may be the same. That is,the second gate G2, the third gate G3 and the first signal line SL1 maybe formed in the same layer. However, the present invention is notlimited thereto. According to other embodiments, the first signal lineSL1 and the first gate G1 may belong to the same layer. In particular,in the present embodiment, the third gate G3 may be a part of the firstsignal line SL1, and the source S may be a part of the second signalline SL2, but the invention is not limited thereto.

Referring to FIG. 3, the method for forming the first active element T1further includes the steps of forming a contact window 230 a and acontact window 215 a in the first insulating layer 210, the secondinsulating layer 220 and the third insulating layer 230, and forming aconductive pattern 270 on the third insulating layer 230. The first gateG, the second gate G2 and the conductive pattern 270 are overlapped witheach other in the normal direction z perpendicular to the substrate 100.For example, the conductive pattern 270 may extend from the thirdinsulating layer 230 to fill into the contact window 230 a and thecontact window 215 a to be electrically connected to the first gate G1and the second gate G2. More specifically, in the embodiment, theconductive pattern 270 directly contacts the first gate G1 and thesecond gate G2. In other words, the first gate G1 and the second gate G2are electrically connected to each other through the conductive pattern270. Moreover, the pixel array substrate 10 may further include thefourth insulating layer 240 covering the source S, the drain D, thesecond signal line SL2, the conductive pattern 270 and the thirdinsulating layer 230. The pixel electrode PE is disposed on the fourthinsulating layer 240 and extends through the fourth insulating layer 240to electrically connect the drain D of the first active element T1 (asshown in FIG. 2).

In the present embodiment, in consideration of conductivity, theconductive pattern 270 is generally made of a metal material. However,the present invention is not limited thereto. According to otherembodiments, the conductive pattern 270 may be made of other conductivematerials, such as an alloy, a nitride of a metal material, an oxide ofa metal material, an oxynitride of a metal material, other suitablematerials, or a stacked layer of a metal material and said otherconductive materials described above. As shown in FIG. 3, in theembodiment, the materials of the conductive pattern 270 and the secondsignal line SL2 may be the same. That is, the conductive pattern 270 andthe second signal line SL2 may be formed in the same layer, but theinvention is not limited thereto.

It is worth mentioning that during an etching process (for example, awet etching process) of forming the contact window 230 a and the contactwindow 215 a, the third insulating layer 230 is etched by the etchant toform the contact window 230 a and expose a portion of the upper surfaceG2 s of the second gate G2. Due to the material of the second gate G2 isdifferent from the materials of the first insulating layer 210, thesecond insulating layer 220, and the third insulating layer 230, thesecond gate G2 is less etched by the etchant than the first insulatinglayer 210, the second insulating layer 220 and the third insulatinglayer 230, and thus the contact window 230 a may partially overlap theupper surface G2 s of the second gate G2 in the normal direction zperpendicular to the substrate 100 (as shown in FIG. 3), and thevertical projection of the region occupied by the contact window 215 aformed by etching the first insulating layer 210 and the secondinsulating layer 220 using the etchant on the substrate 100 is locatedwithin the vertical projection of the region occupied by the contactwindow 230 a on the substrate 100.

As shown in FIG. 1, in this embodiment, the semiconductor pattern SC mayhave a first segment SCa and a second segment SCb, and the secondsegment SCb is connected between the first segment SCa and the secondsignal line SL2. The third gate G3 may be overlapped with the firstsegment SCa in the normal direction z perpendicular to the substrate100, and the first gate G1 and the second gate G2 both may be overlappedwith the second segment SCb in the normal direction z perpendicular tothe substrate 100. In other words, the first channel region CR1 and thesecond channel region CR2 of the semiconductor pattern SC arerespectively located in the first segment SCa and the second segmentSCb.

Referring to FIG. 1 and FIG. 2, the first channel region CR1 has a firstlength L1 in the extending direction of the first segment SCa (i.e., thedirection y), and the second channel region CR2 has a second length L2in the extending direction of the second segment SCb (i.e., thedirection x). In this embodiment, the first length L1 of the firstchannel region CR1 may be equal to the second length L2 of the secondchannel region CR2. In other words, the ratio of the second length L2 ofthe second channel region CR2 to the first length L1 of the firstchannel region CR1 is substantially 1. From another point of view, sincethe channel region of the semiconductor pattern SC (for example, thefirst channel region CR1 and the second channel region CR2) is formed byperforming the ion doping process with the gate (for example, the secondgate G2 and the third gate G3) as mask, so the length of the channelregion may be substantially equal to the width of the gate. In otherwords, in the present embodiment, the width of the second gate G2 in thedirection x may be equal to the width of the third gate G3 in thedirection y. Moreover, the first segment SCa of the semiconductorpattern SC has a width W5 in the direction x, the second segment SCb hasa width W6 in the direction y, and the width W5 of the first segment SCamay be equal to the width W6 of the second segment SCb. In other words,the ratio of the width W6 of the second segment SCb to the width W5 ofthe first segment SCa is substantially 1.

Further, in order to increase the aperture ratio of the pixel structurePX (or the layout space of the driving circuit) and avoid short circuitbetween the driving lines, in some embodiments, the shortest distance dlbetween the vertical projection of the region occupied by the contactwindow 230 a on the substrate 100 and the vertical projection of theregion occupied by the contact window 225 a on the substrate 100 may bein the range of 2.25 μm to 6 μm. In the present embodiment, in order toprevent the semiconductor pattern SC from degrading under the long-timeillumination of the backlight to improve the reliability of the activeelement, the pixel array substrate 10 may further include a lightshielding pattern 280. The light shielding pattern 280 is locatedbetween the substrate 100 and the semiconductor pattern SC. In thepresent embodiment, the light shielding pattern 280 may be overlappedwith the first channel region CR1 of the semiconductor pattern SC in thenormal direction z perpendicular to the substrate 100.

It is worth mentioning that, in this embodiment, the first gate G1 has awidth W3 in the extending direction of the second segment SCb (i.e., thedirection x), the second gate G2 has a width W4 in the extendingdirection of the second segment SCb (i.e., the direction x), and thewidth W3 of the first gate G1 may be greater than the width W4 of thesecond gate G2, so that the second channel region CR2 of thesemiconductor pattern SC can be prevented from degrading under thelong-time illumination of the backlight to improve the reliability ofthe active element. However, the present invention is not limitedthereto. In some embodiments, the width W3 of the first gate G1 may besubstantially equal to the width W4 of the second gate G2. In thisembodiment, the materials of the light shielding pattern 280, the firstgate G1 and the third signal line SL3 may be the same. That is, thelight shielding pattern 280, the first gate G1 and the third signal lineSL3 may be belong to the same layer, but the invention is not limitedthereto.

In the following, other embodiments will be described to explain thepresent invention in detail, in which the same components will bedenoted by the same reference numerals, and the description of the sametechnical content will be omitted. For the omitted part of thedescription, please refer to the foregoing embodiments, and details arenot described below.

FIG. 4 is a top view of a pixel array substrate 20 according to anotherembodiment of the present invention. Referring to FIG. 4, the pixelarray substrate 20 of the present embodiment differs from the pixelarray substrate 10 of FIG. 1 in that: in the pixel array substrate 20,the width W3 of the first gate G1 and the width W4 of the second gate G2are smaller than the width W7 of the third gate G3. From another pointof view, in the pixel array substrate 20, the second length L2 of thesecond channel region of the semiconductor pattern SC (i.e., the regionwhere the semiconductor pattern SC overlaps the second gate G2) may besmaller than the first length L1 of the first channel region of thesemiconductor pattern SC (i.e., a region in which the semiconductorpattern SC overlaps the third gate G3). Specifically, in the presentembodiment, the ratio of the second length L2 of the second channelregion to the first length L1 of the first channel region may be between0.5 and less than 1. Moreover, in the pixel array substrate 20, thewidth W6 of the second segment SCb of the semiconductor pattern SC maybe smaller than the width W5 of the first segment SCa. Specifically, inthe present embodiment, the ratio of the width W6 of the second segmentSCb to the width W5 of the first segment SCa may be between 0.5 and lessthan 1.

Further, the first active element T1A includes the first gate G1 and thesecond gate G2 disposed on the upper and lower sides of thesemiconductor pattern SC, so that the operating electrical properties ofthe active element can be effectively improved, for example, the leakagecurrent generated when the active element is turned off can be reduced,and the driving current of the active element when it is turned on canbe increased. Therefore, from another point of view, the design marginof the active element can be increased, for example, the width of thegate in the extending direction of the semiconductor pattern (i.e., thelength of the channel region) can be shortened, and the width of thesemiconductor pattern (i.e., the width of the channel region) can bereduced. As such, the aperture ratio of the pixel structure PX or thelayout space of the driving circuit can be increased.

FIG. 5 is a top view of a pixel array substrate 30 according to stillanother embodiment of the present invention. Referring to FIG. 5, thedifference between the pixel array substrate 30 of the presentembodiment and the pixel array substrate 10 of FIG. 1 mainly lies in:the number of the gates of the first active element T1 of the pixelarray substrate 30 is two (i.e., the first gate G1 and the second gateG2), and each pixel structure PX further includes a second activeelement T2, a third active element T3 and a fourth signal line SL4. Itshould be noted that the present invention does not limit the number ofpixel structures and signal lines by the content disclosed in thedrawings. In some embodiments, the number of pixel structures and signallines may be adjusted according to different design requirements.

In the embodiment, the third active element T3 is electrically connectedbetween the first active element T1 and the pixel electrode PE, and thesecond active element T2 is electrically connected to the first signalline SL1, the second signal line SL2 and the third active element T3. Indetail, the source S and the drain D of the first active element T1 arerespectively electrically connected to the fourth signal line SL4 andthe source S of the third active element T3, the drain D and the gate Gof the third active element T3 are respectively electrically connectedto the pixel electrode PE and the drain D of the second active elementT2, and the source S and the gate G of the second active element T2 arerespectively electrically connected to the second signal line SL2 andthe first signal line SL1.

In particular, in the pixel array substrate 30, the second signal lineSL2 and the third signal line SL3 electrically connected to the samepixel structure PX are respectively located on opposite sides of thatpixel structure PX, which differs from the pixel array substrate 10 and20 of the foregoing embodiments. In detail, in the pixel array substrate30, the source S of the second active element T2 and the first gate G1(or the second gate G2) of the first active element T1 located in thesame pixel region PA are respectively electrically connected to thesecond signal line SL2 and the third signal line SL3. From another pointof view, the third signal line SL3 electrically connected to the firstactive element T1 of one of the two adjacent pixel structures PX and thesecond signal line SL2 electrically connected to the second activeelement T2 of another one of the two adjacent pixel structures PX areoverlapped with each other in the normal direction z perpendicular tothe substrate 100.

In this embodiment, the fourth signal line SL4 may have a high voltagelevel, and in the pixel array substrate 30, the second active elementT2, the third active element T3 and the first active element T1 can beturned on through the first signal line SL1, the second signal line SL2and the third signal line SL3, so that the driving current transmittedby the fourth signal line SL4 flows into the pixel electrode PE to drivethe display medium (not shown) disposed on the pixel electrode PE, thedisplay medium is, for example, a luminescent material layer. Moreover,in the pixel array substrate 30, at least one of the first activeelement T1, the second active element T2 and the third active elementsT3 can be turned off through at least one of the first signal line SL1,the second signal line SL2 and the third signal line SL3, so that thedriving current transmitted by the fourth signal line SL4 is preventedfrom flowing into the pixel electrode PE.

For example, the pixel structures PX connected to the same first signalline SL1 (e.g., a scan line) include a first pixel structure and asecond pixel structure. During a scan period, when the gate G of thesecond active element T2 of the first pixel structure and the gate G ofthe second active element T2 of the second pixel structure are appliedwith a positive bias through the same first signal line SL1, the gate Gof the third active element T3 of the first pixel structure and the gateG of the third active element T3 of the second pixel structure arerespectively applied with another positive bias through thecorresponding second signal lines SL2. At this time, the first gate G1and the second gate G2 of the first pixel structure can be applied withanother positive bias through the corresponding third signal line SL3 toallow the driving current transmitted by the corresponding fourth signalline SL4 to flow into the pixel electrode PE of the first pixelstructure; while the first gate G1 and the second gate G2 of the secondpixel structure can be applied with a negative bias through thecorresponding third signal line SL3 to not allow the driving currenttransmitted by the corresponding fourth signal line SL4 to flow into thepixel electrode PE of the second pixel structure.

In other words, the pixel structures PX connected to the same firstsignal line SL1 can be respectively charged (or discharged) at differentupdate frequencies through the settings of the first gate G1, the secondgate G2 and the third signal line SL3. For example, a portion of thepixel structures PX can be driven at an update frequency of 60 Hz, whileanother portion of the pixel structures PX can be driven at an updatefrequency of 1 Hz. As a result, the power consumption of the pixel arraysubstrate is able to be reduced.

In this embodiment, each pixel structure PX is exemplarily illustratedby taking the architecture of three active elements (i.e., 3T) as anexample, and does not represent that the present invention is limitedthereto. In other embodiments, each pixel structure PX may be a 1T1Carchitecture, a 3T1C architecture, a 3T2C architecture, a 4T1Carchitecture, a 4T2C architecture, a 5T1C architecture, a 5T2Carchitecture, a 6T1C architecture, a 6T2C architecture, a 7T2Carchitecture or any possible architectures.

In summary, in the pixel array substrate of one embodiment of thepresent invention, the pixel structures connected to the same firstsignal line can be respectively driven at different update frequenciesthrough the settings of the third signal line, the first gate and thesecond gate, which helps to reduce the power consumption of the pixelarray substrate. Further, by overlapping the third signal line with thesecond signal line, the aperture ratio of the pixel structure and thelayout space of the driving circuit can be increased. Moreover, in thefirst active element, the semiconductor pattern is interposed betweenthe first gate and the second gate, thereby effectively improving theoperating electrical properties of the active element.

Although the disclosure has been described with reference to the aboveembodiments, it will be apparent to those of ordinary skill in the artthat modifications to the described embodiments may be made withoutdeparting from the spirit of the disclosure. Accordingly, the scope ofthe disclosure will be defined by the attached claims and not by theabove detailed descriptions.

What is claimed is:
 1. A pixel array substrate, comprising: a substrate;a first signal line and a second signal line are disposed on thesubstrate, wherein the first signal line intersects the second signalline; a third signal line disposed on the substrate, wherein the thirdsignal line intersects the first signal line, and in a normal directionperpendicular to the substrate, the second signal line is overlappedwith the third signal line; a first active element comprising asemiconductor pattern, a first gate, and a second gate, wherein thesemiconductor pattern is located between the first gate and the secondgate, and the second gate is overlapped with the first gate, and thefirst gate is electrically connected to the third signal line; and aconductive pattern electrically connected to the first gate and thesecond gate, wherein the conductive pattern, the first gate and thesecond gate are overlapped with each other in the normal direction. 2.The pixel array substrate of claim 1, wherein the first active elementfurther comprises a third gate electrically connected to the firstsignal line, and the semiconductor pattern is electrically connected tothe second signal line.
 3. The pixel array substrate of claim 2, whereinthe semiconductor pattern has a first segment extending in a firstdirection and a second segment extending in a second direction, whereinin the normal direction, the first segment is overlapped with the thirdgate, and the second segment is overlapped with the first gate and thesecond gate.
 4. The pixel array substrate of claim 3, wherein the firstsegment of the semiconductor pattern has a first channel region, and thesecond segment of the semiconductor pattern has a second channel region,the first channel region has a first length in the first direction, thesecond channel region has a second length in the second direction, and aratio of the second length to the first length is between 0.5 and
 1. 5.The pixel array substrate of claim 3, wherein the first segment has afirst width perpendicular to the first direction, and the second segmenthas a second width perpendicular to the second direction, and a ratio ofthe second width to the first width is between 0.5 and
 1. 6. The pixelarray substrate of claim 3, wherein the first gate has a first width inthe second direction, and the second gate has a second width in thesecond direction, and the first width is greater than the second width.7. The pixel array substrate of claim 1, wherein the semiconductorpattern is overlapped with the second signal line and the third signalline in the normal direction, the semiconductor pattern is locatedbetween the second signal line and the third signal line, and thesemiconductor pattern is electrically connected to the second signalline.
 8. The pixel array substrate of claim 1, further comprising: afirst insulating layer disposed between the first gate and thesemiconductor pattern; and a second insulating layer disposed betweenthe second gate and the semiconductor pattern, wherein a first contactwindow is disposed in the first insulating layer and the secondinsulating layer, and the first contact window is overlapped with thefirst gate.
 9. The pixel array substrate of claim 8, further comprising:a third insulating layer disposed on the second gate and covering aportion of a surface of the second gate, wherein a second contact windowis disposed in the third insulating layer, the second contact isoverlapped with the first gate and the second gate, and the conductivepattern extends from the third insulating layer to fill into the secondcontact window and the first contact window and contacts the first gateand the second gate.
 10. The pixel array substrate of claim 9, whereinthe first contact window does not align with the second contact window.11. The pixel array substrate of claim 9, wherein a third contact windowis disposed in the second insulating layer and the third insulatinglayer, and a portion of the second signal line is filled with the thirdcontact window to electrically connect to the semiconductor pattern. 12.The pixel array substrate of claim 11, wherein a shortest distancebetween a vertical projection of a region occupied by the first contactwindow on the substrate and a vertical projection of a region occupiedby the third contact window on the substrate is between 2.25 μm and 6μm.
 13. The pixel array substrate of claim 1, further comprising asecond active element, wherein the first active element and the secondactive element are respectively located on opposite sides of the secondsignal line, and the second active element is electrically connected tothe first signal line and the second signal line.
 14. The pixel arraysubstrate of claim 1, wherein a vertical projection area of the secondsignal line on the substrate is smaller than a vertical projection areaof the third signal line on the substrate.
 15. The pixel array substrateof claim 1, further comprising a light shielding pattern located betweenthe semiconductor pattern and the substrate, wherein the light shieldingpattern and the third signal line belong to the same layer.
 16. Thepixel array substrate of claim 1, wherein the conductive pattern and thesecond signal line belong to the same layer.
 17. The pixel arraysubstrate of claim 1, wherein the first gate and the third signal linebelong to the same layer.
 18. The pixel array substrate of claim 1,wherein the second gate and the first signal line belong to the samelayer.
 19. The pixel array substrate of claim 1, wherein the material ofthe third signal line comprises molybdenum and molybdenum oxide.